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Transactions on Cryptographic Hardware and Embedded Systems
Scopus
ISSN 2569-2925 · Ruhr-Universität Bochum · 821 artikel di indeks
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Artikel Jurnal Teks lengkap
Sota Voce: Low-Noise Sampling of Sparse Fixed-Weight Vectors
Many post-quantum cryptosystems require generating an n-bit binary vector with a prescribed Hamming weight ω, a process known as fixed-weight sampling. When ω = O(n), we call this dense fixed-weight sampling, which commonly appears in lattice-based cryptosystems, like those in the NTRU family. In…
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Artikel Jurnal Teks lengkap
PipFHE: Resource-Efficient Privacy-Preserving Deep CNN Inference via Padded Batch Packing and Channel Merging over FHE
Privacy-Preserving Machine Learning (PPML) has demonstrated great potential in data-sensitive industries, driving the development of low-latency CNN architectures using Fully Homomorphic Encryption (FHE). However, existing methods encounter two primary challenges when processing large image…
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S5: Combining white-box countermeasures to resist state-of-the-art attacks
In white-box cryptography, the DCA attack broke early encoding-based countermeasures, leading to the utilization of masking schemes against a surge of local attacks. The recent filtering attack from CHES 2024 broke the last viable masking scheme from CHES 2021, which resisted both computational and…
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Turtle Walk: Stopping Timing Attack on NoC
In recent years, several countermeasures such as Gossip NoC, Ironhide, SurfNoC, Adaptive Routing, Random Arbitration, and Guard NoC have been proposed to mitigate micro-architectural timing attacks on Network-on-Chip (NoC) architectures. However, the security of these countermeasures has not been…
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Artikel Jurnal
RainHash2.0: Hardware- and Arithmetization-friendly Hash Function
Zero-knowledge (ZK) proof systems have developed rapidly in recent years, with hash functions as one of their central building blocks. Since these often dominate the prover cost, circuit-friendly hash function design has become an active research area. Most hash proposals target prime fields…
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SoK: From Silicon to Netlist and Beyond
Hardware serves as the root of trust in modern computing systems, making Hardware Reverse Engineering (HRE) essential for security assurance—from design verification and supply-chain integrity to vulnerability discovery. We scope HRE to netlist recovery and its subsequent analysis, spanning the…
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SAFEDT: A Privacy-Preserving Decision Tree Inference Framework Using Homomorphic Encryption
With the increasing application of machine learning in sensitive domains such as healthcare, the demand for privacy-preserving techniques in decision tree inference has grown urgent. Traditional decision trees, when executed in untrusted environments, pose a risk of exposing sensitive data to…
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Bit2Watt: A Cyber–Physical Vulnerability Exploiting GPU Workloads Across Power and Computing Infrastructure
Modern data centers increasingly rely on large-scale GPU clusters and on-site renewable energy resources, resulting in a tightly coupled cyber–physical system between computing workloads and power-electronic-dominated grids. In this paper, we reveal Bit2Watt, a previously unexplored vulnerability…
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Area Efficiency in Constant-Cycle Schemes
Boolean masking is a widely used countermeasure to protect hardware implementations against side-channel attacks. However, combining security with low latency remains challenging, since in many composed masked designs the latency increases with the number of cascaded non-linear operations…
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Breaking the Area Limit of Composable Gadgets
With the continuous advancement of side-channel attack techniques, the demand for high-order masking has been steadily increasing. However, as the masking order grows, the area overhead quickly becomes a critical bottleneck for cryptographic primitives in the IoT environment. Classical…
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Multiplicative Integer Division over Integer-wise TFHE
This paper proposes homomorphic multiplicative division algorithms over integer-wise TFHE. These algorithms compute an approximate reciprocal of the divisor and use it to evaluate division, based on Rodeheffer’s integer Newton- Raphson (NR) algorithm. In addition to the homomorphic adaptation of…
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Low-Stack HAETAE for Memory-Constrained Microcontrollers
We present a low-stack implementation of the module-lattice signature scheme HAETAE, targeting microcontrollers with 8 kB–16 kB of available SRAM. On such devices, peak stack usage is often the binding constraint, and HAETAE’s hyperball-based sampler, large transient polynomial vectors, and…
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Artikel Jurnal
Power Analysis and Countermeasures on the MiMC Block Cipher
Modern zero-knowledge (ZK), fully homomorphic encryption (FHE) and Multi-party Computation (MPC) protocols have motivated research interest in Arithmetization-Oriented (AO) cryptographic primitives. The use of these protocols on embedded platforms requires consideration for protection against…
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Trustless Delegation of Vector Commitment Construction in Resource-Constrained Settings
Many data types, such as video and audio, consist of sequential elements where both integrity and order are essential for authenticity. In practice, verifiers often access only partial sequences due to privacy or bandwidth constraints, motivating the use of vector commitments (VCs) for verifiable…
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Efficient and Compact High-order Masking Raccoon on Memory Constrained Devices
Raccoon, presented at CRYPTO 2024, is a provably secure lattice-based signature scheme featuring an O(d log d) masking overhead. Although it did not advance beyond the first-round of NIST’s additional call for post-quantum digital signatures, Raccoon remains a promising candidate due to its low…
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Refined Approx-SVP Rank Reduction Conditions and Adaptive Lattice Reduction for MSIS Security Estimation
The security of lattice-based cryptography relies critically on the concrete hardness of the approximate shortest vector problem (Approx-SVP). For cryptographic-sized instances, existing Approx-SVP rank reduction conditions may be overly aggressive, as they implicitly assume access to a large…
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Artikel Jurnal
Coupling Leakage in Theory and Practice
With the widespread adoption of Field Programmable Gate Arrays (FPGAs) in security-critical industries such as defense and telecommunications, ensuring the confidentiality of sensitive data processed by these devices has become paramount. Side-Channel Analysis (SCA) poses a significant threat…
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Pipelining FALCON’s Gaussian sampler
We present the first fully pipelined implementation of FALCON’s Gaussian sampler SamplerZ, which has previously dominated signature-generation time. The design mitigates the latency cost of rejection sampling by launching a new sampling attempt every clock cycle. On the ZCU104 FPGA, our accelerator…
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SQISign on ARM
We present the first vectorized implementation of SQIsign for highperformance Arm architectures. SQIsign is a promising candidate in the NIST On-Ramp Digital Signatures Call Round 2 thanks to its most compact key and signature sizes. However, its performance remains a bottleneck, in particular in…
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Artikel Jurnal
High-Throughput GPU Design and Implementation of MAYO with Matrix Computation Reordering
With the rapid development of quantum computing, traditional digital signature schemes face increasing security threats. MAYO is a post-quantum digital signature scheme based on the hardness of the multivariate quadratic problem. Owing to its compact signature size, reduced public key, and flexible…